1. Field of the Invention
The present disclosure generally relates to the field of fabricating microstructures, such as integrated circuits, and, more particularly, to a technique for determining alignment accuracy and pattern placement precision during patterning processes.
2. Description of the Related Art
The fabrication of microstructures, such as integrated circuits, requires tiny regions of precisely controlled size to be formed in a material layer of an appropriate substrate, such as a silicon substrate, a silicon-on-insulator (SOI) substrate, or other suitable carrier materials. These tiny regions of precisely controlled size are generated by patterning the material layer using lithography, etch, implantation, deposition, oxidation processes and the like, wherein typically, at least in a certain stage of the patterning process, a mask layer may be formed over the material layer to be treated to define these tiny regions. Generally, a mask layer may consist of or may be formed by means of a layer of photoresist that is patterned by a lithographic process, typically a photolithography process. During the photolithography process, the resist may be spin-coated onto the substrate surface and then selectively exposed to radiation through a corresponding lithography mask, such as a reticle, thereby imaging the reticle pattern into resist layer to form a latent image therein. After developing the photoresist, depending on the type of resist, i.e., positive resist or negative resist, the exposed portions or the non-exposed portions are removed to form the required pattern in the layer of photoresist. Based on this resist pattern, actual device patterns may be formed by further manufacturing processes, such as etch, implantation, anneal processes and the like. Since there is a constant demand for reducing the dimensions of the patterns in sophisticated integrated microstructure devices in view of performance enhancement, the process tools and process recipes used for patterning device features have to meet very stringent requirements with regard to resolution and overlay accuracy. In this respect, resolution is considered as a measure for specifying the consistent ability to print minimum size images under conditions of predefined manufacturing variations. One important factor in improving the resolution is the lithographic process, in which patterns contained in the photo mask or reticle are optically transferred to the substrate via an optical imaging system. Therefore, great efforts are made to steadily improve optical properties of the lithographic system, such as numerical aperture, depth of focus and wavelength of the light source used.
The quality of the lithographic imagery is extremely important in creating very small feature sizes. Of at least comparable importance is the accuracy with which an image can be positioned on the surface of the substrate. Typically, microstructures, such as integrated circuits, are fabricated by sequentially patterning material layers, wherein features on successive material layers bear a spatial relationship to one another. Each pattern formed in a subsequent material layer has to be aligned to a corresponding pattern formed in the previously patterned material layer within specified registration tolerances. These registration tolerances are caused by, for example, a variation of a photoresist image on the substrate due to non-uniformities in such parameters as resist thickness, baking temperature, exposure dose and time and development conditions. Furthermore, non-uniformities of the etch processes can also lead to variations of the etched features. In addition, there exists an uncertainty in overlaying the image of the pattern of the current material layer to the etched or otherwise defined pattern of the previously formed material layer while photolithographically transferring the image of the photo mask onto the substrate. Several factors contribute to an imperfect ability of the imaging system to overlay two layers, such as imperfections within a set of masks, temperature differences at the different times of exposure, a limited registration capability of the alignment tool and, as a major contribution to alignment errors, imperfections of the exposure tool itself, such as lens distortions, and distortions caused by the alignment hardware, such as the substrate holder, and the like. The situation becomes even worse when different exposure tools are used for defining subsequent device layers, since then the inherent errors in the exposure tool and related components may vary between the different tools.
Although the same exposure tool might be used for imaging critical device layers, in practice, such restrictions may not allow an efficient overall process flow in a complex manufacturing environment, which typically comprises a plurality of lithography tools for the same device layer. As a result, the dominant criteria for determining the minimum feature size that may finally be obtained are the resolution for creating features in individual substrate layers and the total overlay error to which the above explained factors contribute.
Therefore, it is essential to continuously monitor the resolution, i.e., the capability of reliably and reproducibly creating the minimum feature size, also referred to as critical dimension (CD), within a specific material layer, and to continuously determine the overlay accuracy of patterns of material layers that have been successively formed and that have to be aligned to each other. For example, when forming a wiring structure for an integrated circuit, respective metal lines and vias, which connect two stacked metal regions, may have to be aligned to each other with strict process margins so as to result in a well-defined overlap, since a significant misalignment may cause a short between actually non-connected lines, thereby possibly creating a fatal device defect, while a reduction of the intended overlap area may cause loss of performance due to increased contact and series resistance. Similar criteria holds true for other device layers, which require well-defined overlap areas in order to ensure proper device function.
For these reasons, great efforts are being made in detecting critical overlap areas, i.e., overlap areas which may cause severe device failures or performance degradations when a corresponding deviation from the initial design is generated upon actually implementing the layout of a respective device layer into the material of the semiconductor device. For example, the layout of the several spatially correlated device layers is designed such that a perfect overlap is ensured, which may involve the application of various test strategies on layout level. During the lithography process and subsequent etch processes, however, significant changes of the initial layout pattern may be caused, for instance, by thinning small structures and the like. Generally, a plurality of fluctuations may occur during the transfer of a specific pattern of a layout layer, which is initially transferred into a reticle or lithography mask and in turn is then used for repeatedly imaging the pattern into a material layer on the semiconductor substrate. As discussed above, the various process steps involved in actually forming a desired pattern in a material layer of the semiconductor device may result in a more or less pronounced introduction of process imperfections, for instance, non-perfect alignment of the lithography mask to the semiconductor substrate, process tolerances caused by the imaging process such as lens aberrations and distortions of the substrate by mechanical stress and the like, and also various tolerances during the etch processes may result in inaccuracies of the resulting device patterns, which in turn may thus result in a reduced overlay accuracy. Since the overlap of respective device features of two subsequent device layers may strongly depend on the finally achieved overlay accuracy, in particular in very small three-dimensional structures, great efforts are being made in identifying critical overlap areas and in enhancing the overall overlay accuracy. For example, on the layout level, complex optical proximity correction techniques may be applied so as to modify the basic geometric layout of at least some device features in order to accommodate certain process variations that may occur, in particular during the imaging process. Although an increased degree of process robustness may be accomplished by using, for example, optical proximity correction techniques, it is nevertheless very difficult to identify the most critical overlap areas since at least two subsequent pattern transfer processes are involved so that a number of possible sources for generating overlay errors may be quite high so as to predict any such process variations by corresponding models used for OPC strategies. On the other hand, a direct observation of critical overlap areas is very difficult, since the underlying layer may not be accessible by well-established inspection techniques, such as scanning electron microscopy.
For these reasons, alternative strategies have been developed in order to identify critical overlap areas. For example, the lateral translation at specific locations within an image field of a lithography tool may be measured on the basis of specifically designed overlay targets. On the basis of the measurement data, a calculation of overlay performance across the entire image field may be performed by using simulation. The result of this procedure, however, strongly depends on the accuracy of the underlying model and the simulation algorithm. In other strategies, overlay performance is measured on the basis of electrical measurement procedures, for instance by forming contact chains and using contacts with a specified degree of “misalignment.” This approach, however, is restricted to special structures and locations inside the image field or chip area. In other cases, yield measurement data may be used for identifying critical overlap areas wherein, however, a direct influence of critical overlap areas on the resulting final production yield is difficult to determine unless corresponding misalignments may be determined on the basis of cross-sectional electron microscopy measurements which, however, are very expensive due to the cross-sectional preparation of the samples. Furthermore, this strategy results in a very long response time so that identification of critical overlap areas may still result in significant yield loss due to a large number of inappropriately processed substrates. Furthermore, as discussed above, any algorithms to identify critical overlap structures in the basic semiconductor design may still require confirmation on substrate level and may not appropriately accommodate various process imperfections.
In view of the situation described above, the present disclosure relates to techniques and systems for identifying critical areas on forming overlapping device features in a semiconductor device while avoiding or at least reducing the effects of one or more of the problems identified above.